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TC3299A
Preliminary Data Sheet
Ethernet PCMCIA Controller + COMBO Transceiver
Features
PCMCIA 2.01 bus interface. Use serial EEPROM 93C56/93C66 to store CIS. NE2000 compatible. IEEE 802.3 compatible. NS8390 Register compatible controller. Endec, UTP, AUI, and included. Auto media select between AUI and UTP. LED support for activity and Link. 100-pin LQFP package. Low Power CMOS process. TC3299A for UTP and AUI interface. IEEE 802.3 standards. TC3299A is compatible to NS8390 controller's register and Novell NE2000 industry Ethernet standard. To store CIS, TC3299A needs EEPROM 93C56/66 in PCMCIA LAN CARD to reduce part cost. Physical media 10BaseT, AUI interface are fully automatic detection. LED driver for Link and other activities are also provided. 10BaseT functional block includes receiver and transmitter, collision, loopback, jabber and link integrity. The Polarity Detection/Correction blocks are also defined as in the standard. TC3299A uses analog Phase Lock Loop method for the Manchester encoding and the decoding method is specified by the IEEE 802.3 specification in the 10Mbit/sec transmission section. A collision detect translator and diagnostic Loopback Capability are also included in the TC3299A. TC3299A is designed for conventional PCMCIA LAN CARD with AUI cable connecting to external MAU. TC3299A provides both UTP and AUI interface for maximum flexibility.
General Description
The TC3299A (EPCC) is designed to reduce parts count and cost for easy implementation of PCMCIA CSMA/CD Local Area Networks. The TC3299A is the integration of the entire bus interface for PCMCIA BUS and which it includes Ethernet controller, Manchester Encoder/decoder, 10BaseT function and AUI interface. It complies with
Block Diagram
PCMCIA BUS
PCMCIA BUS Interface Logic and Drivers
TC3299 Transmit and Receive Control Logic
DMA Buffer Control Logic
93C56/66 for CIS & Node ID
Manchester Encoder and Decoder
External SRAM
Physical Medium Auto-MUX
TP Interface
AUI interface
Block Diagram of TC3299A
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( TC3299A OPTION )
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TC3299A
Preliminary Data Sheet
Table Of Contents
Features ..............................................................................................................................................................1 General Description ............................................................................................................................................1 Block Diagram.....................................................................................................................................................1 Table Of Contents ...............................................................................................................................................2 Pin Configuration ................................................................................................................................................3 1 Pin Description ............................................................................................................................................4 2 Functional Description ................................................................................................................................7 2.1 Power On Configuration....................................................................................................... 9 3 Configuration Registers ............................................................................................................................ 11 3.1 EPCC Core Registers ........................................................................................................ 12 4 Absolute Maximum Ratings......................................................................................................................25 5 Standard Test Conditions..........................................................................................................................25 6 D.C. Characteristics................................................................................................................................25 7 Physical Dimensions.................................................................................................................................26
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August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
Pin Configuration
MMM MMA AA AA111 89012 M C A MMM S MM 1ARW0DD 30** *01 MMMMMMVG DDDDDDCNXX 234567CD21 C D V CC DO +I
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MA7 MA6 MA5 MA4 VCC MA14 MA3 MA2 MA1 EECS SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 GND IO16* INPACK* INT* VCC NC GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 44 43 42 LLED TXTX+ AGND RXRX+ AVDD RDRD+ TD+ TDLYTDTDLY+ GND VCC RST SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 WAIT*
TC3299A 100pin LQFP
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
26 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
WS EA *0
S A 1
S A 2
S A 3
S A 4
S A 5
S A 6
S A 7
S A 8
S A 9
AGNDDNNVCI IORG CNC I OCCCEOOEEN LD C1RW*GD E *** * D
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August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
1 Pin Description
Pin No. Symbol I/O I I/O I/O Description These address signal lines of PCMCIA Bus are used to select a register to be read or written and attribute memory enable. Register Access, with DMA inactive, SD0-SD7 pins are used to read/write register data. SD8-SD15 pins are invalid during this state. Remote DMA Bus Cycle, SD0-SD15 pins contain packet data. Direction of transfer is depended on Remote read/write. Reset pin. RST is active high and placed EPCC in a reset mode immediately. During falling edge, the EPCC controller loads the configuration from MD0-7, MA0-13. This pin is set low to insert wait states during Remote DMA transfer. REG* is an active low input used to determine whether a lost access is to Attribute memory (The first 1K) or to common memory (above 1K). If REG* is set to low the access is to attribute memory, while REG* is set to high the access is to common memory. REG* is also asserted low for all accesses to the TC3299A's IO Registers. Read Strobe: Strobe from host to read internal registers or Remote DMA read. Write Strobe: Strobe from host to write internal registers or Remote DMA write. Host memory read strobe. The attribute memory can be read when OE* and REG* are both at low state. While for Common memory to be accessed, OE* should be set to low state and REG* should set to high state. OE* REG* Attribute Memory Low Low Common Memory Low High Host memory write strobe. After Power reset, if TC3299A is configured to memory write enable, then 2 types of memories are written as defined below: WE* REG* Attribute Memory Low Low Common Memory Low High Active low signal, asserted if the host access TC3299A internal register or Remote DMA read cycle. IO16* is driven by EPCC to support host 16 bits access cycle. Interrupt:Indicates that the EPCC requires host attention after reception, transmission or completion of DMA transfer. Card enable 1, are active low signals driven by the host. These signals provide a card select based on an address decode (decode by the host).
ISA Bus Interface Pins 2-11 SA0-SA9 27-34 93-86 SD0-SD7 SD8-SD15
35
RST
I
26 24
WAIT* REG*
O I
21 22 23
IOR* IOW* OE*
I I I
1
WE*
I
96 95 97 20
INPACK* IO16* INT* CE1*
O O O I
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TC3299A
Preliminary Data Sheet
Pin No. Symbol I/O I/O Description When RST is inactive these pins can be used to access external memory. When RST is active configuration is loaded with the data value on MD0-MD7 pins. When RST is inactive These pins drive the memory address bus during DMA access cycle. When RST is active configuration is loaded with the data value on MA0-MA13 pins. Memory Bus Read: Strobes data from the buffer memory into the EPCC via the memory data bus. Memory Bus Write: Strobes data from the EPCC into the external buffer memory via the memory data bus. Buffer RAM chip select, active low. EEPROM chip select. It is asserted when to access EEPROM. Connected to EEPROM data output pin. Connected to EEPROM data input pin. Memory Interface Pins 65-58 MD0-7
79-70 MA4-13 81 MA14 82-84, 69 MA3-1, MA0 68 67 66 85 16 15 MR* MW* CS0* EECS DO DI
I/O
O O O O I O
Pin No.
Symbol
I/O I O
Description Crystal or External Oscillator Input:20 MHz Crystal Feedback Output:Used in crystal connection only.
Clock interface Pins 54 X1 55 X2
Pin No.
Symbol
I/O O O I I O O
Description 10BaseT differential transmit drivers. 10BaseT wave predistortion control differential outputs. 10BaseT differential receive input port. Filter input for data recover analog PLL. Link integral LED driver. During Link loss, output high. During loading EEPROM data, used as Serial clock to the EEPROM. When power on reset, This pin must stay at high level. Otherwise, TC3299A will enter internal test mode. Active LED:(default) MA8 is open, when power reset. It functions as active indication LED driver. CLED: MA8 pull down during power reset. It works as Collision LED driver.
Network Interface Pins 41,39 TD+/38,40 42,43 51 50 12 TDLY+/RD+/VCOI LLED ACLED
Pin No.
Symbol
I/O
Description
Network Interface Pins(TC3299A option) 45,46 RX+/RXI 10Base5, Receiver input pair to controller. 48,49 52,53 TX+/TXCD+/CDO I 10Base5, Transmit output pair from controller. 10Base5, Collision input pair to controller.
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TC3299A
Preliminary Data Sheet
Pin No. Symbol Power Supply Pins 19,36,57,8 VCC 0,98 13,25,37,5 GND 6,94, 100 44 AVDD 47 AGND I/O Description +5V DC is required. It is suggested that a decoupling capacitor be connected between VCC and GND. Power for analog Phase Lock Loop circuit of EPCC.
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August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
2 Functional Description
The EPCC controller is a highly integrated jumperless configurable Ethernet controller. It integrates the function of the following blocks: TC3299A Ethernet Controller Core and Media Access Control logic. 1. PCMCIA 2.0 Bus interface containing all logics require to connect the TC3299A core to a packet buffer RAM and the PCMCIA Bus. 2. Serial EPROM interfaces, which loads Ethernet ID and Configuration Registers into the EPCC. 3. Physical media interface contains Encoder/Decoder with a 10BaseT Twisted Pair interface. I/O PORT ADDRESS MAPPING This is compatible with Novell's NE2000. The base I/O address of EPCC Controller is configured by Configuration Registers (either upon power up or writing to this register by software). At that address the following structure appears. Base + 00H TC3299A Core Registers Base + 0FH Base +10H Data Transfer Port Base + 17H Base + 18H Reset Port Base + 1FH The registers within this area are 8 bits wide, but the data transfer port is 16 bits wide. By accessing the data transfer port (using I/O instructions) the user can transfer data to or from the EPCC Controller's internal memory. The EPCC Controller' internal memory map is as shown below. D15 0000H PROM 001FH Reserved 4000H 8K x 16 Buffer RAM 7FFFH EPCC Core's Memory Map PROM Location 00h 01h 02h 03h
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D7
D0
Location Contents ETHERNET ADDRESS 0 ETHERNET ADDRESS 1 ETHERNET ADDRESS 2 ETHERNET ADDRESS 3
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TC3299A
Preliminary Data Sheet
PROM Location 04h 05h 06-0Dh 0E,0Fh 10-15h 16-1Dh 1E-1Fh Location Contents ETHERNET ADDRESS 4 ETHERNET ADDRESS 5 RESERVED 57h ETHERNET ADDRESS 0-5 RESERVED 42h
Details of PROM Map EPCC Controller actually has a 64K address range but only does partial decoding on these devices. The PROM data is mirrored at all decodes up to 40000H and the entire map is repeated at 80000H. To access either the PROM or the RAM the user must initiate a Remote DMA transfer between the I/O port and memory. Remote Read/Write Cache: The EPCC Controller includes 4 words cache internally. On a remote read the EPCC Controller moves data from external memory buffer to the internal cache buffer; the EPCC moves data continuously until the cache buffer is full. On a remote write the system can writes data into the cache buffer until the 4 words cache buffer is full. PCMCIA CIS Structures & Decode Function: The TC3299A supports access to 1K of attribute memory. Attribute memory is defined by the PCMCIA standard to be comprised of the card's information structure and four 8-bits Card Configuration Registers. These four registers are contained in the TC3299A. The attribute Memory (only even address can be accessed) map for a PCMCIA card is shown below. 7 (Reserved) (Reserved) CCR1 (TC3299A) CCR0 (TC3299A) Reserved Card's information structure 0 3FEH 3FCH 3FAH 3F8H 3F0H-3F6H 2EEH 02 00
Card Configuration Registers 0(R/W) (CCR0) 7 RESET 6 XX 5 IOEN 4 XX 3 XX 2 XX 1 PJ1 0 PJ0
RESET : When this bit is set 1, a software reset to TC3299A. IOEN : When this bit is set 1, the I/O operation is enabled.
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TC3299A
Preliminary Data Sheet
PJ1,0 : If MA12 isn't pulled low during power on reset, despite of the value of PJ1,0, TC3299A response to I/O access at the I/O base address 300h, 320h, 340h, 360h. otherwise, I/O base Map as below: PJ1 PJ0 I/O base Map 0 0 300h 0 1 320h 1 0 340h 1 1 360h PJ1,0 : Reserved
Configuration Registers 1 (R) (CCR1) 7 XX IREQ XX 6 XX 5 XX 4 XX 3 XX 2 XX 1 IREQ 0 XX
: Controller interrupt status : Reserved
2.1
Power On Configuration
The EPCC Controller configures itself after a RST signal is applied. When a Power-On-Reset occurs the EPCC Controller latches the values on the configuration pins and uses these to configure the internal registers and options. Internally these pins contain pull-up resistance. If these configuration pins are unconnected the default logic will be applied. The configuration registers are loaded from the memory data bus when RST goes inactive. A Power-On-Reset also causes the EPCC Controller to load the internal PROM store from the EEPROM, which can take up to 3 ms. This occurs after Config-Regs (Configuration registers?) have completed. If EECONFIG is high (MA9 pull down) the configuration data loaded on the falling edge of RST will be overwritten by the data read from the serial EEPROM. Regardless of the level on EECONFIG the PROM store will always be loaded with data from the serial EEPROM during the time specified as EELOAD. Figure 1 shows how the RESET circuitry operates.
VCC
RESET
Regload
EEload
The EPCC Controller users an 93C56/66, The programmed contents of the EEPROM is shown as following. ...... ...... 16H 14H 12H
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D15 CIS byte n ........ ........ CIS byte 3
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D0 CIS byte n-1 ........ ........ CIS byte 2
August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
10H 0FH 0EH 08H 07H 04H 03H 02H 01H 00H D15 CIS byte 1 Not Used Config. B Reserved 42H 57H Reserved Reserved E'net Address 5 E'net Address 3 E'net Address 1 D0 CIS byte 0 Config. C Config. A Reserved 42H 57H Reserved bit (0) : 8 bit enable bit (7:1) : Reserved E'net Address 4 E'net Address 2 E'net Address 0
EEPROM Programming Map **03H bit(0):If MA11 is pulled low during power on reset and this bit is set high. TC3299A can work at NE2000's 8-bit mode. Storing and Loading Configuration from EEPROM: If the EECONFIG is set high (MA9 pull low) during boot up, the EPCC Controller's configuration is determined by the EEPROM, before the PROM data is read The configuration data is stored within the address 0EH of the EEPROM's address space. Configuration Register A and B are located in the address 0EH. To write this configuration into the EEPROM, The user can program register in EPCC's address 02H of page 3. This operation will work regardless of the level on EECONFIG.
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TC3299A
Preliminary Data Sheet
3 Configuration Registers
Configuration Register A (R/W) To prevent any accidental write of this register, it is "hidden" behind a previously unused register. Register 0AH in the EPCC Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register A can be read at that address and can be written to by following a read to 0AH with a write to 0AH. If any other ENCC Controller register accesses take place between the read and the write then the write to 0AH will access the Remote Byte Count Register 0. 7 XX 6 FREAD 5 XX 4 XX 3 XX 2 XX 1 XX 0 XX
FREAD :The ENCC Controller supports 4 words Remote DMA read/write cache. When this bit is set high,Remote DMA cache control will be enabled. XX :Reserved Configuration Register B (R/W) To prevent any accidental write of this register, it is "hidden" behind a previously unused register. Register 0BH in the EPCC Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register B can be read at that address and can be written to by following a read to 0BH with a write to 0BH. If any other ENCC Controller register accesses take place between the read and the write then the write to 0BH will access the Remote Byte Count Register 1. 7 XX 6 LINK 5 XX 4 XX 3 2 1 0 IO16CONGDLINK PHYS1 PHYS0
PHYS1,0 : PHYSICAL LAYER INTERFACE 0 0 1 1 0 1 0 1 AUTO DETECT Reserved 10Base5 10BaseT
In auto detect mode. For TC3299A, MA10 open for 10BaseT or 10Base5 auto-detect. GDLINK : When this bit is high, to disable link test pulse generation and integrity checking. IO16CON : When this bit is set high the Controller generates IO16* after REG* and CE1* active. If low this output is generated only on address decode. LINK : When this bit is high, link test integrity checking is Goood. Otherwise, indicate link signal Loss. XX : Reserved. Configuration Register C Can be load data from EEPROM only 7 XX 6 XX 5 XX 4 XX 3 XX 2 XX 1 CRDASEL 0 XX
CRDASEL : When this bit is high. CRDA0, CRDA1 increasing address control by internal cache state machine.
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TC3299A
Preliminary Data Sheet
XX When this bit is low, CRDA0, CRDA1 increasing address control by remote read command. : Reserved.
Hardware Configuration These functions are configured during a power on RESET. EECFG(MA9) : MA9 should be pulled down to enable CFGA and CFGB load from EEPROM. AUICB(MA10) : In media physic auto detect mode. It should be opened for TC3299A. ENG8(MA11) : If MA11 is pull down and EEPROM 03H bit(0) is setting high, EPCC can work at NE2000 8 bit mode. Otherwise it will work at 16-bit mode. IOSP(MA12) : If MA12 is pull down, enable I/O base 300H,320H,340H, and 360H separately. If MA12 is not pulled low, despite of the value of PJ1, 0, TC3299A responses to I/O access at the I/O base address 300h, 320h, 340h, and 360h. DCD5BIT(MA13) : Regardless of MA12 setting, once MA13 is pulled down, TC3299A only decodes input address SA4 - SA0 and can only work at I/O Base address. Programming Register (R/W) The EPCC Controller enable software (driver) programming EEPROM or testing interrupt signal through this register directly. It is located at EPCC's core register Page3 base+02H. 7 EESEL 6 XX 5 XX 4 READ 3 CS 2 SK 1 DI 0 DO(r) ATTRDIS
EESEL,CS,SK,DI,DO : The software can read or program serial EEPROM directly through these pins. EESEL should be set high before starting the EEPROM read/write. READ : EPCC can reload CFGA,CFGB and internal PROM if this bit is set high. When reload state is completed, READ will be cleared to low. ATTRDIS : Attribute and common memory access will be disable if it is programmed to high. NOTE : DO : read only ATTRDIS : write only
3.1
EPCC Core Registers
All registers are 8-bit wide and mapped into two pages which are selected in the Command Registers (PS0,PS1). Pins A0-A3 are used to address registers within each page. Page 0 register are those registers which are commonly accessed during EPCC Controller operation while Page 1 registers are used primarily for initialization. The registers are partitioned to avoid having to perform two read/write cycles to access commonly used registers. Register Assignments: A0-A3 RD Page 0 Address Assignments (PS1=0,PS0=0) 00H Command (CR) 01H Current Local DMA Address 0 (CLDA0) 02H Current Local DMA Address 1 (CLDA1) 03H Boundary Pointer (BNRY)
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WR Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY)
August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
A0-A3 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH RD Transmit Status Register (TSR) Number of Collisions Register (NCR) FIFO (FIFO) WR Transmit Page Start Address (TPSR) Transmit Byte Count Register 0 (TBCR0) Transmit Byte Count Register 1 (TBCR1) Interrupt Status Interrupt Status Register (ISR) Register (ISR) Current Remote DMA Remote Start Address Address 0(CRDA0) Register 0 (RSAR0) Current Remote DMA Remote Start Address Address 1 (CRDA1) Register 1 (RSAR1) Config. Register A (CFGA) Remote Byte Count Register 0 (RBCR0) Config. Register B (CFGB) Remote Byte Count Register 1 (RBCR1) Receive Status Register (RSR) Receive Configuration Register (RCR) Tally Counter 0 (Frame alignment Errors) Transmit Configuration (CNTR0) Register (TCR) Tally Counter 1 Data Configuration (CRC errors) (CNTR1) Register (DCR) Tally Counter 2 (Missed Interrupt Mask Packet Errors) (CNTR2) Register (IMR) WR Command (CR) Physical Address Register 0(PAR0) Physical Address Register 1(PAR1) Physical Address Register 2(PAR2) Physical Address Register 3(PAR3) Physical Address Register 4(PAR4) Physical Address Register 5(PAR5) Current Page Register (CURR) Multicast Address Register 0(MAR0) Multicast Address Register 1(MAR1) Multicast Address Register 2(MAR2) Multicast Address Register 3(MAR3) Multicast Address Register 4(MAR4) Multicast Address Register 5(MAR5) Multicast Address Register 6(MAR6) Multicast Address Register 7(MAR7)
A0-A3 RD Page 1 Address Assignments (PS1=0,PS0=1) 00H Command (CR) 01H Physical Address Register 0(PAR0) 02H Physical Address Register 1(PAR1) 03H Physical Address Register 2(PAR2) 04H Physical Address Register 3(PAR3) 05H Physical Address Register 4(PAR4) 06H Physical Address Register 5(PAR5) 07H Current Page Register (CURR) 08H Multicast Address Register 0(MAR0) 09H Multicast Address Register 1(MAR1) 0AH Multicast Address Register 2(MAR2) 0BH Multicast Address Register 3(MAR3) 0CH Multicast Address Register 4(MAR4) 0DH Multicast Address Register 5(MAR5) 0EH Multicast Address Register 6(MAR6) 0FH Multicast Address Register 7(MAR7)
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TC3299A
Preliminary Data Sheet
A0-A3 RD Command(CR) Current Local DMA Address 0(CLDA0) Current Local DMA Address 1(CLDA1) Remote Next Packet Pointer Reserved Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WR Page 2 Address Assignments(PS1=1,PS0=0) 00H Command(CR) 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Page Start Register (PSTART) Page Stop Register (PSTOP) Remote Next Packet Pointer Transmit Page Start Address(TPSR) Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Receive Configuration Register(RCR) Transmit Configuration Register(TCR) Data Configuration Register(DCR) Interrupt mask Register(IMR)
Note: Page 2 registers should only be accessed for diagnostic purposes. They should not be modified during normal operation. Page 3 Reserved should never be modified. A0-A3 RD Command(CR) Reserved Programming Reg. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WR
Page 3 Address Assignments(PS1=1,PS0=1) 00H Command(CR) 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Reserved Programming Reg. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
REGISTER DESCRIPTIONS: Command Register (CR) (Read/Write) The Command Register is used to initiate transmissions, enable or disable Remote DMA operations and to select register pages. To issue a command the microprocessor sets the corresponding bit(s) (RD2, RD1, RD0, and TXP). Further commands may be overlapped, but with the following rules:(1) if a transmit command overlaps with a remote DMA operation, bits RD0, RD1, and RD2 must be maintained for the remote DMA command when setting the TXP bit. Note, if a remote DMA command is re-issued when giving the transmit command, the DMA will complete immediately if the remote byte count register have not been reinitialized. (2) If a remote DMA operation overlaps a transmission, RD0, RD1, and RD2 may be written with the desired values and a "0"to this bit has no effect. (3) A remote write DMA may not overlap remote read operation or visa versa. Either of these operations must either complete or be aborted before the other operation may start. Bits PS1, PS0, RD2, and STP may be set any time. 7 PS1 Bit D0 6 PS0 Symbol STP 5 RD2 4 RD1 3 RD0 2 TXP 1 STA 0 STP
D1
STA
D2
TXP
D3-D5
RD0-RD2
Description Stop: Software reset command, takes the controller offline, no packets will be received or transmitted. Any reception of transmission in progress will continue to completion before entering the reset state. To exit this state, the STP bit must be reset. The software reset is executed only when the RST bit in the ISR being set to a 1. STP powers up high. Start: This bit is used to active the EPCC core after either power up, or when the EPCC cord has been placed in a reset mode by software command. STA power up low. Transmit Packet: This bit must be set to initiate transmission of a packet. TXP is internally reset either after the transmission is completed or aborted. This bit should be set only after the Transmit Byte Count and Transmit Page Start registers have been programmed. TXP powers up low. Remote DMA Command: These three encoded bits control operation of the Remote DMA channel. RD2 can be set to about any Remote DMA command in progress. The Remote Start Addresses are not restored to the starting address if the Remote DMA is aborted. RD2 powers up high. RD2 RD1 RD0 0 0 0 Not Allowed 0 0 1 Remote Read 0 1 0 Remote Write (Note) 0 1 1 Send Packet 1 X X Abort/Complete Remote DMA (Note) Page Select: Three two encoded bits select which register page is to be accessed with addresses A0-3. PS1 0 0 1 1 PS0 0 1 0 1 Register Page 0 Register Page 1 Register Page 2 Register Page 3
D6,D7
PS0,PS1
Data Configure register (DCR) This Register is used to program the EPCC for 8 or 16-bit memory interfaces, select byte ordering in 16-bit applications and establish FIFO thresholds. The DCR must be initialized prior to load the Remote Byte count Registers.
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TC3299A
Preliminary Data Sheet
7 Bit D0 6 FT1 Symbol WTS 5 FT0 4 ARM 3 LS 2 Description Word Transfer Select 0: Selects byte-wide DMA transfers. 1: Selects word-wide DMA transfers Note: when word-wide mode is selected, up to 32k words are addressable; A0 remains low. Reserved Reserved Loopback Select 0: Loopback mode selected. Bits D1,D2 of the TCR must also be programmed for Loopback mode selected. 1: Normal Operation. Auto-Initialize Remote 0: Send Command not executed, all packets removed from Buffer Ring under program control. 1: Send Command executed, Remote DMA auto-initialized to remove packets from Buffer Ring. FIFO Threshold Select: Encoded FIFO threshold. During reception, the FIFO threshold indicates the number of bytes (or words) the FIFO has filled serially from the network before the FIFO is emptied onto memory bus. RECEIVE THRESHOLDS FT1 0 0 1 1 FT0 0 1 0 1 Word Wide 1 Word 2 Word 4 Word 6 Word Byte Wide 2 Bytes 4 Bytes 8 Bytes 12 Bytes 1 0 WTS
D1 D2 D3
LS
D4
ARM
D5,D6
FT0,FT1
During transmission, the FIFO threshold indicates the number of bytes (of words) the FIFO has filled from the Local DMA before being transferred to the memory. Thus, the transmission threshold is 16 bytes less the receive threshold. Transmit configuration Register (TCR) The transmit configuration establishes the actions of the transmitter section of the EPCC during transmission of a acket on the network, LB1 and LB0 power up as 0. 7 Bit D0 6 Symbol CRC 5 4 OFST 3 ATD 2 LB1 Description Inhibit CRC 0: CRC appended by transmitter 1: CRC inhibited by transmitter Encoded Loopback Control: These encoded configuration bits set the type of loopback that should be performed. Notethat loopback in mode 2 sets the LPBK pin high, this places the TC3096 in loopback mode and that D3 of the DCR must be set to zero for loopback operation.
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1 LB0
0 CRC
D1,D2
LB0,LB1
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TC3299A
Preliminary Data Sheet
Bit Symbol Description LB1 LB0 Mode0 0 0 Normal Operation (LPBK=0) Mode1 0 1 Internal Loopback (LPBK=0) Mode2 1 0 External Loopback (LPBK=1) Mode3 1 1 External Loopback (LPBK=0) Auto Transmit Disable: This bit allows another station to disable the EPCC'S transmitter by transmission of a particular multicast packet. The transmitter can be re-enabled by resetting this bit or by reception of a second particular multicast packet. 0: Normal Operation 1: Reception of multicast address hashing to 62 bit disables transmitter, reception of multicast address hashing to bit 63 enables transmitter. Collision Offset Enable: This bit modifies the back off algorithm to allow prioritization of nodes. 0: Backoff Logic implements normal algorithm. 1: Forces Backoff algorithm modification to 0 to 2mim(3+n,10) slot times for first three collisions, Then follows standard backoff. (For first three collisions station has higher average backoff delay making a low priority mode.) Reserved Reserved Reserved
D3
ATD
D4
OFST
D5 D6 D7
-
Transmit Status Register (TSR) This register records events that occur on the media during transmission of a packet. It is cleared when the host initiates the next transmission. All bits remain low unless the event that corresponds to a particular bit occurs during transmission. Each transmission should be followed by a read of this register. The contents of this register are not specified until after the first transmission. 7 OWC Bit D0 D1 D2 6 CDH 5 FU 4 CRS 3 ABT 2 COL 1 0 PTX
Symbol PTX COL
D3
ABT
D4
CRS
D5
FU
Description Packet Transmitted: Indicates transmission without error (No excessive collisions or FIFO underrun) (ABT="0",FU="0"). Reserved Transmit Collided: Indicates that the transmission collided at least once with another station on the network. The number of collisions is recorded in the Number of Collisions Registers. (NCR). Transmit Aborted: Indicates the EPCC aborted transmission because of excessive collisions. (Total number of transmissions including original transmission attempt equals 16). Carrier Sense Lost: This bit is set when carrier is lost during transmission of the packet. Carrier Sense is monitored from the end of Preamble/ Synch until TXE is dropped. Transmission is not aborted on loss of carrier. FIFO Underrun: If the EPCC cannot gain access of the bus before the FIFO empties, this bit is set. Transmission of the packet will be aborted.
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TC3299A
Preliminary Data Sheet
D6 CDH CD Heartbeat: Failure of the transceiver to transmit a collision signal after transmission of a packet will set this bit. The Collision Detect (CD) heartbeat signal must commence during the first 6.4us of the Interframe Gap following a transmission. In certain collisions, the CD Heartbeat bit will be set even though the transceiver is not performing the CD heartbeat test. Out of Window Collision: Indicates that a collision occurred after a slot time (51.2us). Transmissions rescheduled as in normal collisions.
D7
OWC
Receive Configuration Register (RCR) This register determines operation of the EPCC during reception of a packet and is used to program what types of packets to accept. 7 Bit D0 6 Symbol SEP 5 MON 4 PRO 3 AM 2 AB Description Save Errored Packets 0: Packets with receive errors are rejected. 1: Packets with receive errors are accepted. Receive errors are CRC and Frame Alignment errors. Accept Runt Packets 0: Packets with fewer than 64 bytes rejected. 1: Packets with fewer than 64 bytes accepted. Accept Broadcast 0: Packets with all 1's broadcast destination address rejected. 1: Packets with all 1's broadcast destination address accepted. Accept Multicast 0: Packets with multicast destination address not checked. 1: Packets with multicast destination address checked. Promiscuous Physical 0: Physical address of node must match the station address programmed in PAR0-PAR5. (Physical address checked) 1: All packets with any physical address accepted. (physical address not checked) Monitor Mode: Enables the receiver to check addresses and CRC on incoming packets without buffering to memory. The missed packet Tally counter will be incremented for each recognized packet. 0: Packets buffered to memory. 1: Packets checked for address match, good CRC and frame Alignment but not buffered to memory. Reserved Reserved 1 AR 0 SEP
D1
AR
D2
AB
D3
AM
D4
PRO
D5
MON
D6 D7
-
Note: D2 and D3 are "OR'd" together, i.e., if D2 and D3 are set the EPCC will accept broadcast and multicast addresses as well as its own physical address. To establish full promiscuous (non discrimination) mode, bits D2, D3 and D4 should be set. In addition the multicast hashing array must be set to all 1's in order to accept all multicast addresses. Receive Status Register (RSR)
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August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
This register records status of the received packet, including information on errors and the type of address match, either physical or multicast. The contents of this register are written to buffer memory by the DMA after reception of a good packet. If packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous packet is received. If packets with errors are to be rejected the RSR will not be written to memory. The contents will be cleared when the next packet arrives. CRC errors, frame Alignment errors and missed packets are counted internally by the EPCC which relinquishes the Host from reading the RSR in real time to record errors for Network Management functions. The contents of this register are not specified until after the first reception. 7 DFR Bit D0 D1 D2 6 DIS Symbol PRX CRC FAE 5 PHY 4 MPA 3 FO 2 FAE 1 CRC 0 PRX
D3 D4
FO MPA
D5
PHY
D6 D7
DIS DFR
Description Packet Received Intact: Indicates packet received without error. (Bits CRC, FAE, FO and MPA are zero for the received packet.) CRC Error: Indicates packet received with CRC error. Increments Tally Counter (CNTR1). This bit will also be set for Frame Alignment errors. Frame Alignment Error: Indicates that the incoming packet did not end on a byte boundary and the CRC did not match at last byte boundary. Increments Tally counter (CNTR0). FIFO Overrun: This bit is set when the FIFO is not serviced causing overflow during reception. Reception of the packet will be aborted. Missed Packet: Set when packet intended for node cannot be accepted by EPCC because of a lack of receive buffers of if the controller is in monitor mode and did not buffer the packet to memory. Increments Tally Counter (CNTR2). Physical/Multicast Address: Indicates whether received packet had a physical or multicast address type 0: Physical Address Match 1: Multicast/Broadcast Address Match Receiver Disabled: Set when receiver disabled by entering Monitor mode. Reset when receiver is re-enabled when exiting Monitor mode. Deferring: Set when CRS or COL inputs are active. If the transceiver has asserted the CD line as a result of the jabber, this bit will stay set indicating the jabber condition.
Note: Following coding applies to CRC and FAE bits FAE 0 0 1 1 CRC 0 1 0 1 Type of Error No error (Good CRC and <6 Dribble Bits) CRC ERROR Legal, will not occur Frame Alignment Error and CRC Error
Interrupt Mask Register (IMR) The interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR). If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zeroes. 7 6 RDCE 5 CNTE 4 OVWE 3 TXEE 2 RXEE 1 PTXE 0 PRXE
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TC3299A
Preliminary Data Sheet
Bit D0 D1 D2 D3 D4 D5 D6 D7 Symbol PRXE PTXE RXEE TXEE OVWE CNTE RDCE Description Packet Received Interrupt Enable: Enables Interrupt when packet received. Packet Transmitted Interrupt Enable: Enables Interrupt when packet is transmitted. Receive Error Interrupt Enable: Enables Interrupt when packet received with error. Transmit Error Interrupt Enable: Enables Interrupt when packet transmission results in error. Over Write Warning Interrupt Enable: Enables Interrupt when Buffer management Logic lacks sufficient buffers to store incoming packet. Counter Overflow Interrupt Enable: Enables Interrupt when MSB of one or more of the Network Tally counters has been set. DMA Complete Interrupt Enable: Enables Interrupt when Remote DMA transfer has been completed. Reserved
Interrupt Status Register (ISR) This register is accessed to determine the cause of an interrupt. Any interrupt can be masked in the interrupt Mask Register (IMR). Individual interrupt bit is cleared by writing a "1" into the corresponding bit of the ISR. The IRQ signal is active as long as any unmasked signal is set, and will not go low until all unmarked bits in this register have been cleared. The ISR must be cleared after power up by writing it with all 1's. 7 RST Bit D0 D1 D2 6 RDC Symbol PRX PTX RXE 5 CNT 4 OVW 3 TXE 2 RXE 1 PTX 0 PRX
D3
TXE
D4 D5 D6 D7
OVW CNT RDC RST
Description Packet Received: Indicates packet received with no errors. Packet Transmitted: Indicates packet transmitted with no errors. Receive Error: Indicates that a packet was received with one or more of the following errors: - CRC Error - Frame Alignment Error - FIFO Overrun - Missed Packet Transmit Error: Set when packet transmitted with one or more of the following errors: - Excessive Collisions - FIFO Underrun Over Write Warning: Set when receive buffer ring storage resources have been exhausted. (Local DMA has reached Boundary Pointer). Counter Over flow: Set when MSB of one or more of the Network Tally Counters has been set. Remote DMA Complete: Set when Remote DMA operation has been completed. Reset Status: A status indicator with no interrupt generated - Set when EPCC enters reset state and is cleared when a start command is issued - Set when a Receive Buffer Ring overflows and is cleared when leaves overflow status. Writing to this bit has no effect and powers up high.
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Confidential. Copyright (c) 2003, IC Plus Corp.
TC3299A
Preliminary Data Sheet
Network Tally Counter Registers (CNTR) Three 8-bit counters are provided for monitoring the number of CRC errors, Frame Alignment Errors and missed packets, The maximum count reached by any counter is 192 (C0H). These registers will be cleared when read by the CPU. The count is recorded in binary in CT0-CT7 of each Tally Register. CNTR0: Monitor the number of Frame Alignment error 7 CT7 7 CT7 7 CT7 6 CT6 6 CT6 6 CT6 5 CT5 5 CT5 5 CT5 4 CT4 4 CT4 4 CT4 3 CT3 3 CT3 3 CT3 2 CT2 2 CT2 2 CT2 1 CT1 1 CT1 1 CT1 0 CT0 0 CT0 0 CT0
CNTR1: Monitor the number of CRC error
CNTR2: Monitor the number of Missed Packets
Number of Collisions Register (NCR) This register contains the number of collisions a node experiences when attempting to transmit a packet. If no collisions are experienced during a transmission attempt, the COL bit of the TSR will be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit in the TSR will not be set and the contents of NCR will be zero. The NCR is cleared after the TXP bit in the CR is set. 7 FIFO Register (FIFO) This is an 8-bit register that allows the CPU to examine the contents of the FIFO after loopback. The FIFO will contain the last 8 data bytes transmitted in the loopback packet. Sequential reads from the FIFO will advance a pointer in the FIFO and allow reading of all 8 bytes. Note that the FIFO should only be read when the EPCC has been programmed in loopback mode. 7 DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 6 5 4 3 NC3 2 NC2 1 NC1 0 NC0
Physical Address Registers (PAR0-PAR5) The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte-wide basis. The bit assignment shown below relates the sequence in PAR0-PAR5 to the bit sequence of the received packet. .. Syn D7 DA7 DA15 DA23 DA31 DA39 DA47 Syn DA0 |------DA1 DA2 DA3 DA4 DestinationAddress D5 DA5 DA13 DA21 DA29 DA37 DA45 D4 DA4 DA12 DA20 DA28 DA36 DA44
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DA5
DA6
DA7 .. --------|-- Source D1 DA1 DA9 DA17 DA25 DA33 DA41 D0 DA0 DA8 DA16 DA24 DA32 DA40
PAR0 PAR1 PAR2 PAR3 PAR4 PAR5
D6 DA6 DA14 DA22 DA30 DA38 DA46
D3 DA3 DA11 DA19 DA27 DA35 DA43
D2 DA2 DA10 DA18 DA26 DA34 DA42
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August 27, 20003 TC3299A-DS-R30
TC3299A
Preliminary Data Sheet
Multicast Address Registers (MAR0-MAR70) The Multicast address registers provide filtering of multicast addresses hashed by the CRC logic. All destination addresses are fed through the CRC logic and as the last bit of the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (FB0-63) in the multicast address register. If the filter bit selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. For some address found to hash to the value 50 (32H), then FB50 in MAR6 should be initialized to "1". All multicast filter bits that correspond to multicast address accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones. MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 D7 FB7 FB15 FB23 FB31 FB39 FB47 FB55 FB63 D6 FB6 FB14 FB22 FB30 FB38 FB46 FB54 FB62 D5 FB5 FB13 FB21 FB29 FB37 FB45 FB53 FB61 D4 FB4 FB12 FB20 FB28 FB36 FB44 FB52 FB60 D3 FB3 FB11 FB19 FB27 FB35 FB43 FB51 FB59 D2 FB2 FB10 FB18 FB26 FB34 FB42 FB50 FB58 D1 FB1 FB9 FB17 FB25 FB33 FB41 FB49 FB57 D0 FB0 FB8 FB16 FB24 FB32 FB40 FB48 FB56
DMA Registers LOCAL DMA TRANSMIT REGISTERS 15 8| 7 0 (TPSR) TRANSMIT PAGE START (TBCR0,1) TRANSMIT BYTE COUNT LOCAL DMA RECEIVE REGISTERS 15 8| 7 (PSTART) PAGE START (PSTOP) PAGE STOP (CURR) CURRENT (BRNY) BOUNDARY 15 8| 7 CURRENT LOCAL DMA ADDRESS
0
0
(CLDA0,1)
REMOTE DMA REGISTERS 15 8| 7 (RSAR0,1) START ADDRESS (RBCR0,1) BYTE COUNT (CRDA0,1)
0
CURRENT REMOTE DMA ADDRESS
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Confidential. Copyright (c) 2003, IC Plus Corp.
TC3299A
Preliminary Data Sheet
(I) Local DMA Transmit Registers Transmit page start register (TPSR): This register points to the assembled packet to be transmitted. Only the eight higher order addresses are specified ince all transmit packets are assembled on 256-byte page boundaries. 7 A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
Transmit byte count register0,1 (TBCR0,TBCR1): These two registers indicate the length of the packet to be transmitted in bytes. The maximum number of transmit bytes allowed is 64k bytes. The EPCC will not truncate transmissions longer than 1500 bytes. TBCR1 TBCR0 7 L15 7 L7 6 L14 6 L6 5 L13 5 L5 4 L12 4 L4 3 L11 3 L3 2 L10 2 L2 1 L9 1 L1 0 L8 0 L0
(II) Local DMA Receive Registers Page start, stop registers (PSTART, STOP): The Page Start and Page stop Registers program the starting and stopping page of the Receive Buffer Ring. Since the EPCC uses fixed 256-byte buffers aligned on page boundaries only the upper eight bits of the start and stop address are specified. PSTART PSTOP 7 A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
Boundary register (BNRY): This register is used to prevent overflow of the Receive Buffer Ring. Buffer management compares the contents of this register to the next buffer address when linking buffers together. If the contents of this register match the next buffer address the local DMA operation is aborted. BNRY 7 A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
(III) Remote DMA registers Remote Start Address Registers (RSAR0,1): Remote Byte Count Registers (RBCR0,1): Remote DMA operations are programmed via the Remote Start Address (RSAR0,1) and Remote Byte Count (RBCR0,1) registers. The Remote Start Address is used to point to the start of the block of data to be transferred and the Remote Byte Count is used to indicate the length of the block (in bytes). RSAR1 RSAR0 7 A15 7 A7 6 A14 6 A6 5 A13 5 A5 4 A12 4 A4 3 A11 3 A3
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2 A10 2 A2
1 A9 1 A1
0 A8 0 A0
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Confidential. Copyright (c) 2003, IC Plus Corp.
TC3299A
Preliminary Data Sheet
RBCR1 RBCR0 7 BC15 7 BC7 6 BC14 6 BC6 5 BC13 5 BC5 4 BC12 4 BC4 3 BC11 3 BC3 2 BC10 2 BC2 1 BC9 1 BC1 0 BC8 0 BC0
Current Page Register: The Buffer Management Logic uses this register internally; it is used as a backup register for reception. CURR contains the address of the first buffer to be used for a packet reception and is used to restore DMA pointers in the event of receive errors. This register is initialized to the same value as PSTART and should not be written to again unless the controller is reset. CURR 7 A15 6 A14 5 A13 4 A12 3 A11 2 A10 1 A9 0 A8
Current local DMA register 0,1 (CLDA0,1): These two registers can be accessed to determine the current Local DMA Address. CLDA1 CLDA0 7 A15 7 A7 6 A14 6 A6 5 A13 5 A5 4 A12 4 A4 3 A11 3 A3 2 A10 2 A2 1 A9 1 A1 0 A8 0 A0
Current Remote DMA Address Registers: The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown below: CRDA1 CRDA0 7 A15 7 A7 6 A14 6 A6 5 A13 5 A5 4 A12 4 A4 3 A11 3 A3 2 A10 2 A2 1 A9 1 A1 0 A8 0 A0
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TC3299A
Preliminary Data Sheet
4 Absolute Maximum Ratings
0C -40C -0.5V TO TO TO 70C 125C 7V AMBIENT TEMPERATURE UNDER BIAS STORAGE TEMPERATURE VOLTAGE ON ALL INPUT AND OUTPUTS WITH RESPECT TO VSS
5
Standard Test Conditions
The characteristics below apply for the following standard test conditions. Unless otherwise noted. All voltages are referred to VSS (0V GROUND), positive current flows into the referred pin. OPERATING TEMPERATURE RANGE POWER SUPPLY VOLTAGE 0C 4.75V TO TO 70C 5.25V
6
D.C.
Symbol VIL VIH IIL IIH VOL VOH ICC
Characteristics
Parameter INPUT LOW VOLTAGE INPUT HIGH VOLTAGE INPUT LOW CURRENT INPUT HIGH CURRENT OUTPUT LOW VOLTAGE OUTPUT HIGH VOLTAGE SUPPLY CURRENT Min. VSS 2.0 2.4 Typ. 35 Max. 0.8 VCC -0.5 20 0.4 Units V V uA uA V V mA Conditions VCC=5V VCC=5V VIN=1.0V VIN=VCC IOL=8.0mA IOH=4.0mA VCC=5V
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TC3299A
Preliminary Data Sheet
7 Physical Dimensions
He E
A2 A1
Y
SYMBOL
MILLIMETER
INCH
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A1 A2 b c D
0.05 1.35 0.17 0.090 13.90 13.90
0.10 1.40 0.22
0.15 1.45 0.27 0.200
0.002 0.053 0.007 0.004 0.547 0.547
0.004 0.055 0.009
0.006 0.057 0.011 0.008
14.00 14.00 0.50
14.10 14.10
0.551 0.551 0.020
0.555 0.555
Hd D
E e Hd He L L1 Y
15.90 15.90 0.45
16.00 16.00 0.60 1.00
16.10 16.10 0.75
0.626 0.626 0.018
0.630 0.630 0.024 0.039
0.634 0.634 0.030
0.08
0
0.003
0
7
7
e
b
0.08(0.003)
M
C
GADE PLANE
0.25
L
Notice Information in this document is subject to change without notice. ICPLUS reserves the rights to change its products at any time. Therefore, the customer is cautioned to confirm with ICPLUS regarding the latest released version before placing orders. ICPLUS devices are NOT designed, intended, authorized, or warranted to be suitable for use in Life-Supporting applications.
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
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